A Novel Time-Area-Power Efficient Single Precision Floating Point Multiplier

In this paper, a single precision IEEE 754 floatingpoint multiplier with high speed and low power is presented. The bottleneck of any single precision floating-point multiplier design is the 24x24 bit integer multiplier. Urdhava Triyakbhyam algorithm of ancient Indian Vedic Mathematics is utilized to improve its efficiency. In the proposed architecture, the 24x24 bit multiplication operation is fragmented to four parallel 12x12 bit multiplication modules. The 12x12 multiplication modules are implemented using small 4x4 bit multipliers. In the unsigned 24x24 bit multiplier architecture, four redundant 4x4 multiplier are provided to enforce the feature of self repairability (to recover from the faults in each 12x12 multiply modules). Reconfigurability at run time is provided for attaining power saving. The multiplier has been designed, optimized and implemented on an FPGA based system. Thus, a highly regular, self-repairable floating point parallel multiplier architecture (which can be directly scaled for larger multiplication) is proposed.